The present invention relates to a method and apparatus for testing printed circuit boards, such as printed circuit cards, ceramic circuit boards, flexible circuit boards and the like, and to an assembly employable in such method and apparatus.
The electronic testing of printed circuit boards or the like requires a number of tests to be conducted. On the one hand, it is desired to test networks or conductors on a given printed circuit board to determine conductivity of such networks or conductors by measuring conductivity from each connection point to each other connection point. On the other hand, it also is desired to measure as accurately as possible, the insulation resistance between individual networks or conductors on the printed circuit board by measuring current flowing between one network and another network or between one conductor and another conductor. Thus, it is desired to ascertain the existence of as high an insulation resistance as possible within the scope of the capabilities of the available electronic testing equipment.
Conventionally, testing of circuit boards in this manner is carried out by establishing electrical connections between connection points of the conductors on the circuit board being tested and contact elements of an array of contact elements with the aid of an adaptor assembly including a plurality of elongated test pins, with test signals being coupled selectively to each contact element of the contact array by electronic switching means such as semiconductor switches, preferably in the form of transistors such as MOS field effect devices.
One problem with this known approach is that transistors of this type do not constitute ideal switches having infinite or zero resistance. Rather, such devices have a relatively low ON resistance higher than zero and a relatively high OFF resistance lower than infinity. As a result, during the measurement of insulation resistance between any two conductors on a given circuit board, there will result the additional detection or sensing of leakage currents which flow through the transistors associated with the connection points of the particular conductor under test, since all of these transistors are connected in parallel between such conductor and ground. The sum total of these leakage currents will not cause any major inconveniences if the conductors involved are relatively short. However, as conductor length increases, the leakage currents may falsify the test result. On typical printed circuit boards, one half to two thirds of the total number of connection points are distributed along many conductors each having a relatively short length, the remainder of the connection points being distributed along conductors associated with a power supply bus and a clock signal line. These latter two conductors usually are very long and have there along a great number of connection points. This results in major problems when it is desired to measure the insulation resistance between such conductors and the other conductors, due to leakage currents caused by the transistors coupled to the connection points of such two conductors. On practical circuit boards, about 30% of the connection points may be on the ground conductor and about 15% of the power supply bus. One reason for this situation is that it is common practice to connect the unused inputs of integrated circuit modules to ground.
Accordingly, if it is desired to measure the insulation resistance between the ground conductor and any other conductor on a printed circuit board, it may be necessary to take into account up to 15,000 transistors connected in parallel in the OFF condition. The leakage currents caused by these 15,000 transistors will be added and will affect the measured test results
It is known to correct for leakage currents by the use of various software. To this end, the leakage current of a "good" sample transistor is measured during programmed initialization, and the leakage current so determined is used for correcting actual measurement results. One disadvantage of this procedure is that it involves unavoidable faults so that the obtainable accuracy is rather low, taking into account the exemplary large number of 15,000 transistors connected in parallel, as indicated above. Even if a small correction error of 1% is assumed, measurements still will include the leakage currents of 150 transistors in the above example. Also, this type of software correction cannot deal with temperature gradients in the testing apparatus which may cause leakage currents to vary with location.